HD6433022F Просмотр технического описания (PDF) - Renesas Electronics

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HD6433022F

16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Renesas Electronics 

5.2.1 System Control Register (SYSCR) ...................................................................... 82

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 84

5.2.3 IRQ Status Register (ISR).................................................................................... 89

5.2.4 IRQ Enable Register (IER) .................................................................................. 90

5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 91

5.3 Interrupt Sources ............................................................................................................... 92

5.3.1 External Interrupts ............................................................................................... 92

5.3.2 Internal Interrupts................................................................................................. 93

5.3.3 Interrupt Vector Table.......................................................................................... 93

5.4 Interrupt Operation............................................................................................................ 96

5.4.1 Interrupt Handling Process................................................................................... 96

5.4.2 Interrupt Sequence ............................................................................................... 101

5.4.3 Interrupt Response Time...................................................................................... 102

5.5 Usage Notes ...................................................................................................................... 103

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 103

5.5.2 Instructions that Inhibit Interrupts........................................................................ 104

5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 104

5.5.4 Usage Notes ......................................................................................................... 104

Section 6 Bus Controller.................................................................................................... 107

6.1 Overview........................................................................................................................... 107

6.1.1 Features................................................................................................................ 107

6.1.2 Block Diagram ..................................................................................................... 108

6.1.3 Pin Configuration................................................................................................. 109

6.1.4 Register Configuration......................................................................................... 109

6.2 Register Descriptions ........................................................................................................ 110

6.2.1 Access State Control Register (ASTCR) ............................................................. 110

6.2.2 Wait Control Register (WCR).............................................................................. 111

6.2.3 Wait State Controller Enable Register (WCER) .................................................. 112

6.2.4 Address Control Register (ADRCR).................................................................... 113

6.3 Operation........................................................................................................................... 115

6.3.1 Area Division ....................................................................................................... 115

6.3.2 Bus Control Signal Timing .................................................................................. 117

6.3.3 Wait Modes.......................................................................................................... 119

6.3.4 Interconnections with Memory (Example) .......................................................... 125

6.4 Usage Notes ...................................................................................................................... 127

6.4.1 Register Write Timing ......................................................................................... 127

6.4.2 Precautions on setting ASTCR and ABWCR* .................................................... 127

Section 7 I/O Ports .............................................................................................................. 129

7.1 Overview........................................................................................................................... 129

Rev.2.00 Mar. 22, 2007 Page xv of xxiv

REJ09B0352-0200

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