HD6433044F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD6433044F

Hitachi Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

Timing of Transition to Hardware Standby Mode

(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10

system clock cycles before the STBY signal goes low, as shown below. RES must remain low

until STBY goes low (minimum delay from STBY low to RES high: 0 ns).

STBY

RES

t1 ≥ 10tcyc

t2 ≥ 0 ns

(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents

do not need to be retained, RES does not have to be driven low as in (1).

Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately

100 ns before STBY goes high.

STBY

RES

t ≥ 100 ns

tOSC

855

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