74F195A Просмотр технического описания (PDF) - Philips Electronics
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74F195A Datasheet PDF : 10 Pages
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Philips Semiconductors
4-bit parallel-access shift register
Product specification
74F195A
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
tS(H)
tS(L)
th(H)
th(L)
tS(H)
tS(L)
th(H)
th(L)
tW(H)
tW(L)
tREC
Setup time, High or Low
J, K and Dn to CP
Hold time, High or Low
J, K and Dn to CP
Setup time, High or Low
PE to CP
Hold time, High or Low
PE to CP
CP Pulse width
High
MR Pulse width
Low
Recovery time
MR to CP
TEST
CONDITION
Waveform 3
Waveform 3
Waveform 4
Waveform 4
Waveform
NO TAG
Waveform 2
Waveform 2
LIMITS
VCC = +5V
Tamb = +25°C
CL = 50pF, RL = 500Ω
VCC = +5V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
MIN TYP MAX
MIN
MAX
2.5
2.5
2.5
2.5
0.0
0.0
1.0
1.0
2.0
2.0
2.5
2.5
0.0
0.0
0.0
0.0
4.5
4.5
4.5
4.5
2.5
3.0
UNIT
ns
ns
ns
ns
ns
ns
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax
CP
VM
VM
tw(H)
tPHL
Q3
VM
VM
tPLH
VM
tPLH
tPHL
Qn
VM
VM
SF00761
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
J, K,
Dn
VM VM
ts(H) th(H)
CP
VM
VM
ts(L)
VM
th(L)
VM
MR
VM
VM
tw(L)
trec
CP
VM
tPHL
Qn
VM
tPLH
Q3
VM
SF00762
Waveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
SERIAL-SHIFT RIGHT
PARALLEL LOAD
PE
VM
VM
ts(H)
th
CP
VM
VM
VM
ts(L)
th
VM
SF00763
Waveform 2. Data Setup and Hold Times
Qn
RESPONSE
Qn=Qn–1
Qn=Dn
SF00764
Waveform 4. Setup and Hold Times, Parallel Enable to Clock
1996 Mar 12
6
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