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FAN5019BMTCX

6-Bit VID Controller 2-4 Phase VR10.X Controller

Fairchild Semiconductor 

PRODUCT SPECIFICATION

FAN5019B

Electrical Specifications

(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)

The • denotes specifications which apply over the full operating temperature range.

Parameter

Error Amplifier

Output Voltage Range

Accuracy

Symbol

VCOMP

VFB

Line Regulation

Input Bias Current

FBRTN Current

Output Current

Gain Bandwidth Product

DC Gain

VID Inputs

Input Low Voltage

ΔVFB

IFB

IFBRTN

IO(ERR)

GBW

VIL(VID)

Input High Voltage

VIH(VID)

Input Current, VID Low

Input Current, VID High

Pull-up Resistance

Internal Pull-up Voltage

IIL(VID)

IIH(VID)

RVID

VID Transition Delay

Time2

“No CPU” Detection

Turn-off Delay Time2

VID Table Select

Vtblsel

Oscillator

Frequency

Frequency Variation

fOSC

fPHASE

Output Voltage

RAMPADJ Pin Accuracy

VRT

VRAMPADJ

RAMPADJ Input Current

Current Sense Amplifier

Offset Voltage

Input Bias Current

Gain Bandwidth Product

IRAMPADJ

VOS(CSA)

IBIAS(CSA)

GBW

Conditions

Min. Typ. Max. Units

• 0.5

3.5

Relative to DAC Setting,

VRM10 • -10

+10

referenced to FBRTN,

VRM9 • -12

+12

CSSUM = CSCOMP,

Test Circuit 3

VCC=10V to 14V

0.05

• -17 -15 -13

•

150 180

FB forced to VOUT – 3%

300 500

COMP = FB ( See Note 2)

20

CCOMP = 10pF ( See Note 2)

77

V

mV

%

µA

µA

µA

MHz

dB

VRM10

VRM9

VRM10

VRM9

VID(X) = 0V

VID(X) = 1.15V

Internal

VRM10

VRM9

VID Code Change to FB Change

•

0.4

V

•

0.8

V

• 0.8

V

• 2.0

V

• -30 -20

µA

• -2

2

µA

• 35

60 115

kΩ

• 1.0 1.15 1.26

V

• 2.2 2.4 2.6

V

• 400

ns

VID Code Change to 11111X to PWM

going low

• 400

To select VRM9 table

•4

To select VRM10 table (becomes VID5) •

ns

V

3.5

V

• 200

4000 kHz

TA = +25°C, RT = 250kΩ, 4-Phase

TA = +25°C, RT = 115kΩ, 4-Phase

TA = +25°C, RT = 75kΩ, 4-Phase

• 155 200 245 kHz

400

kHz

600

kHz

RT = 100kΩ to GND

• 1.9 2.0 2.1

V

VRAMPADJ = Vdac = +2K • (Vin–Vdac)/

(Rr+2k) @ 20µA

• -50

+50 mV

Current into RAMPADJ pin

0

100

µA

CSSUM–CSREF, Test Circuit 1

COMP = FB ( See Note 2)

• -1.5

+1.5 mV

• -50

+50

nA

10

MHz

Notes:

1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control

2. Guaranteed by design – NOT tested in production.

REV. 1.0.0 Jul/15/05

5

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