AN-8027 Просмотр технического описания (PDF) - Fairchild Semiconductor
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AN-8027 Datasheet PDF : 17 Pages
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AN-8027
To properly attenuate the twice line frequency ripple in
VRMS, it is typical to set the poles around 10~20Hz.
The resistor RIAC should be large enough to prevent
saturation of the gain modulator as:
2VLINE.BO ⋅ G MAX < 159μ A
RIAC
(17)
where VLINE.BO is the brownout protection line voltage,
GMAX is the maximum modulator gain when VRMS is 1.08V
(which can be found in the datasheet), and 159µA is the
maximum output current of the gain modulator.
(Design Example) The brownout protection threshold is
1.05V (VRMS-UVL) and 1.9V (VRMS-UVH), respectively.
Then, the scaling down factor of the voltage divider is:
RRMS 3
= VRMS −UVL ⋅ π
RRMS1 + RRMS 2 + RRMS 3 VLINE.BO 2 2
= 1.05 ⋅ π = 0.0162
72 2 2
Then the startup of the PFC stage at the minimum line
voltage is checked as:
V ⋅ LINE.MIN 2RRMS3 = 85 ⋅ 2 ⋅ 0.0162 = 1.95 > 1.9V
RRMS1 + RRMS 2 + RRMS 3
The resistors of the voltage divider network are selected
as RRMS1=2MΩ, RRMS1=200kΩ, and RRMS1=36kΩ.
To place the poles of the low pass filter at 15Hz and
22Hz, the capacitors are obtained as:
CRMS1
=
2π ⋅
1
fP1 ⋅ RRMS 2
=
1
2π ⋅15 ⋅ 200 ×103
= 53nF
CRMS 2
≅
2π
⋅
1
fP2 ⋅ RRMS 3
=
2π
1
⋅ 22 ⋅36 ×103
=
200nF
The condition for Resistor RIAC is:
RIAC
>
2VLINE.BO
159 ×10−6
⋅ GMAX
=
2 ⋅72 ⋅9
159 ×10−6
= 5.8M Ω
Therefore, 6MΩ resistor is selected for RIAC.
[STEP-4] PFC Inductor Design
The duty cycle of boost switch at the peak of line voltage is
given as:
DLP
=
VBOUT − 2VLINE
VBOUT
(18)
Then, the maximum current ripple of the boost inductor at
the peak of line voltage for low line is given as:
ΔIL =
2VLINE.MIN ⋅ VBOUT − 2VLINE ⋅ 1
LBOOST
VBOUT
f SW
(19)
The average of boost inductor current over one switching
cycle at the peak of the line voltage for low line is given as:
I L. AVG
=
2 POUT
VLINE.MIN ⋅η
(20)
Therefore, with a given current ripple factor
(KRB=ΔIL/ILAVG), the boost inductor value is obtained as:
LBOOST
=
V2
LINE .MIN
⋅η
K RB ⋅ POUT
⋅ VBOUT − 2VLINE
VBOUT
⋅
1
fSW
The maximum current of boost inductor is given as:
(21)
IL PK
=
I L.AVG
⋅ (1+
KRB )
2
=
2 POUT
VLINE.MIN ⋅η
⋅ (1+
KRB )
2
(22)
(Design Example) With the ripple current
specification (40%), the boost inductor is obtained as:
LBOOST
=
V2
LINE.MIN
⋅η
⋅ VBOUT
−
2VLINE
K RB ⋅ POUT
VBOUT
⋅
1
f SW
= 852 ⋅ 0.82 ⋅ 387 − 2 ⋅85 ⋅ 10−3 = 524μ H
0.4 ⋅300
387
65
The average of boost inductor current over one
switching cycle at the peak of the line voltage for low
line is obtained as:
I L. AVG
= 2POUT
VLINE.MIN ⋅η
=
2 ⋅ 300
85 ⋅ 0.82
= 6.09A
The maximum current of the boost inductor is given as:
IL PK
= 2POUT
VLINE.MIN ⋅η
⋅ (1+
KRB )
2
= 2 ⋅ 300 ⋅ (1+ 0.4 ) = 7.31A
85⋅ 0.82
2
[STEP-5] PFC Output Capacitor Selection
The output voltage ripple should be considered when
selecting the PFC output capacitor. Figure 14 shows the
twice line frequency ripple on the output voltage. With a
given specification of output ripple, the condition for the
output capacitor is obtained as:
CBOUT
>
2π ⋅
I BOUT
f ⋅V LINE BOUT ,RIPPLE
(23)
where IBOUT is nominal output current of boost PFC stage
and VBOUT,RIPPLE is the peak-to-peak output voltage ripple
specification.
The hold-up time also should be considered when
determining the output capacitor as:
CBOUT
>
PBOUT ⋅ tHOLD
V2
BOUT
− VBOUT ,MIN 2
(24)
where PBOUT is nominal output power of boost PFC stage,
tHOLD is the required holdup time, and VBOUT,MIN is the
allowable minimum PFC output voltage during hold-up time.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
7
www.fairchildsemi.com
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