AD7715ARU-5REEL Просмотр технического описания (PDF) - Analog Devices
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AD7715ARU-5REEL Datasheet PDF : 40 Pages
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AD7715
AVDD = 3 V to 5 V, DVDD = 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK IN = 1 MHz to
2.4576 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Min
Typ
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit1
Negative Full-Scale Calibration Limit1
Offset Calibration Limit2
Input Span2
0.8 ×
VREF/GAIN
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage (AD7715-3)
3
AVDD Voltage (AD7715-5)
4.75
DVDD Voltage
3
Power Supply Currents
AVDD Current
Max
Unit
(1.05 ×
V
VREF)/GAIN
−(1.05 ×
V
VREF)/GAIN
−(1.05 ×
V
VREF)/GAIN
V
(2.1 × VREF)/GAIN V
3.6
V
5.25
V
5.25
V
0.27
mA
0.6
mA
DVDD Current4
Power Supply Rejection5
Normal-Mode Power Dissipation4
0.5
mA
1.1
mA
0.18
mA
0.4
mA
0.5
mA
0.8
mA
Depends on gain6
dB
Normal-Mode Power Dissipation4
1.5
mW
2.65
mW
3.3
mW
5.3
mW
Standby (Power-Down) Current7
Standby (Power-Down) Current7
3.25
mW
5
mW
6.5
mW
9.5
mW
20
μA
10
μA
Conditions/Comments
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
For specified performance
For specified performance
For specified performance
AVDD = 3.3 V or 5 V. gain = 1 to 128 (fCLK IN = 1 MHz) or
gain = 1 or 2 (fCLK IN = 2.4576 MHz)
Typically 0.2 mA; BUF bit of the setup register = 0
Typically 0.4 mA; BUF bit of the setup register = 1, AVDD
= 3.3 V or 5 V; gain = 32 or 128 (fCLK IN = 2.4576 MHz)3
Typically 0.3 mA; BUF bit of the setup register = 0
Typically 0.8 mA; BUF bit of the setup register = 1
Digital inputs = 0 V or DVDD; external MCLK IN
Typically 0.15 mA. DVDD = 3.3 V. fCLK IN = 1 MHz
Typically 0.3 mA. DVDD = 5 V. fCLK IN = 1 MHz
Typically 0.4 mA. DVDD = 3.3 V. fCLK IN = 2.4576 MHz
Typically 0.6 mA. DVDD = 5 V. fCLK IN = 2.4576 MHz
AVDD = DVDD = 3.3 V; digital inputs = 0 V or DVDD; external
MCLK IN
BUF bit = 0. all gains 1 MHz clock
BUF bit = 1. all gains 1 MHz clock
BUF bit = 0. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
BUF bit = 1. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
AVDD = DVDD = 5 V. digital inputs = 0 V or DVDD; external
MCLK IN
BUF bit = 0; all gains 1 MHz clock
BUF bit = 1; all gains 1 MHz clock
BUF bit = 0; gain = 32 or 128 @ fCLK IN = 2.4576 MHz
BUF bit = 1; gain = 32 or 128 @ fCLK IN = 2.4576 MHz
External MCLK IN = 0 V or DVDD. typically 10 μA; VDD = 5 V
External MCLK IN = 0 V or DVDD. typically 5 μA; VDD = 3.3 V
1 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs
all 0s.
2 These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND − 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
3 Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency.
4 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the
crystal or resonator type (see the Clocking and Oscillator Circuit section).
5 Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
notches of 20 Hz or 60 Hz.
6 PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical.
7 If the external master clock continues to run in standby mode, the standby current increases to 50 μA typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator
type (see the Standby Mode section).
Rev. D | Page 7 of 40
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