AD7715ARZ-5REEL(RevE) Просмотр технического описания (PDF) - Analog Devices
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AD7715ARZ-5REEL Datasheet PDF : 40 Pages
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AD7715
Data Sheet
TIMING CHARACTERISTICS
DVDD = 3 V to 5.25 V; AVDD = 3 V to 5.25 V; AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless
otherwise noted.
Table 4.
Parameter1, 2
fCLKIN3, 4
tCLK IN LO
tCLK IN HI
t1
t2
Read Operation
t3
t4
t55
t6
t7
t8
t96
t10
Write Operation
t11
t12
t13
t14
t15
t16
Limit at TMIN, TMAX
(A Version)
400
2.5
0.4 × tCLK IN
0.4 × tCLK IN
500 × tCLK IN
100
0
120
0
80
100
100
100
0
10
60
100
100
120
30
20
100
100
0
Unit
kHz min
MHz max
ns min
ns min
ns nom
ns min
Conditions/Comments
Master clock frequency: crystal oscillator or externally supplied for specified
performance
Master clock input low time; tCLK IN = 1/fCLK IN
Master clock input high time
DRDY high time
RESET pulsewidth
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
DRDY to CS setup time
CS falling edge to SCLK rising edge setup time
SCLK falling edge to data valid delay
DVDD = 5 V
DVDD = 3.3 V
SCLK high pulsewidth
SCLK low pulsewidth
CS rising edge to SCLK rising edge hold time
Bus relinquish time after SCLK rising edge
DVDD = +5 V
DVDD = +3.3 V
SCLK falling edge to DRDY high7
ns min
ns min
ns min
ns min
ns min
ns min
CS falling edge to SCLK rising edge setup time
Data valid to SCLK rising edge setup time
Data valid to SCLK rising edge hold time
SCLK high pulsewidth
SCLK low pulsewidth
CS rising edge to SCLK rising edge hold time
1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 8 and Figure 9.
3 CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw
higher current than specified and possibly become uncalibrated.
4 The AD7715 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although take care that
subsequent reads do not occur close to the next output update.
TO
OUTPUT
PIN
50pF
ISINK (800µA AT DVDD = 5V
100µA AT DVDD = 3.3V)
+1.6V
ISOURCE (200µA AT DVDD = 5V
100µA AT DVDD = 3.3V)
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. E | Page 8 of 40
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