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LTC1287CCJ8

3V Single Chip 12-Bit Data Acquisition System

Linear Technology 

TEST CIRCUITS

CS

Voltage Waveforms for ten

LTC1287

CLK

DOUT

0.6V

ten

B11

LTC1287 TC07

APPLICATI S I FOR ATIO

The LTC1287 is a data acquisition component which

contains the following functional blocks:

1. 12-bit successive approximation capacitive A/D

converter

2. Analog multiplexer (MUX)

3. Sample-and-hold (S/H)

4. Synchronous, half-duplex serial interface

5. Control and timing logic

DIGITAL CONSIDERATIONS

Serial Interface

The LTC1287 communicates with microprocessors and

other external circuitry via a synchronous, half-duplex,

three-wire serial interface (see Operating Sequence). The

clock (CLK) synchronizes the data transfer with each bit

being transmitted on the falling CLK edge. The LTC1287

does not require a configuration input word and has no DIN

pin. It is permanently configured to have a single differen-

tial input and to operate in unipolar mode. A falling CS

initiates data transfer. The first CLK pulse enables DOUT.

After one null bit, the A/D conversion result is output on the

DOUT line with a MSB-first sequence followed by a LSB-

first sequence. With the half duplex serial interface the

DOUT data is from the current conversion. This provides

easy interface to MSB- or LSB-first serial ports. Bringing

CS high resets the LTC1287 for the next data exchange.

Logic Levels

The logic level standards for this supply range have not

been well defined. What standards that do exist are not

universally accepted. The trip point on the logic inputs of

the LTC1287 is 0.28 × VCC. This makes the logic inputs

compatible with HC-type levels and processors that are

tCYC

CS

CLK

Hi-Z

DOUT

tSMPL

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

tCONV

Figure 1. LTC1287 Operating Sequence

tSMPL

LTC1287 F01

1287fa

7

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