EDS1232CASE Просмотр технического описания (PDF) - Elpida Memory, Inc

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EDS1232CASE

128M bits SDRAM

Elpida Memory, Inc 

Relationship Between Frequency and Minimum Latency

Parameter

-1A

Frequency (MHz)

100

tCK (ns)

Symbol

10

Active command to column command

(same bank)

lRCD

2

Active command to active command

(same bank)

lRC

7

Active command to precharge command

(same bank)

lRAS

5

Precharge command to active command

(same bank)

lRP

2

Write recovery or data-in to precharge

command (same bank)

lDPL

2

Active command to active command

(different bank)

lRRD

2

Self refresh exit time

lSREX

1

Last data in to active command

(Auto precharge, same bank)

lDAL

4

Self refresh exit to command input

lSEC

7

Precharge command to high impedance

(CL = 2)

lHZP

2

(CL = 3)

lHZP

3

Last data out to active command

(Auto precharge, same bank)

Last data out to precharge

(early precharge)

(CL = 2)

lAPR

1

lEP

–1

(CL = 3)

lEP

–2

Column command to column command

lCCD

1

Write command to data in latency

DQM to data in

DQM to data out

lWCD

0

lDID

0

lDOD

2

CKE to CLK disable

lCLE

1

Register set to active command

lMRD

2

/CS to command disable

lCDD

0

Power down exit to command input

lPEC

1

Notes: 1. lRCD to lRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

EDS1232CASE

Unit

Notes

tCK

1

tCK

1

tCK

1

tCK

1

tCK

1

tCK

1

tCK

2

tCK

= [lDPL + lRP]

tCK

= [lRC]

3

tCK

tCK

tCK

tCK

tCK

tCK

tCK

tCK

tCK

tCK

tCK

tCK

tCK

Data Sheet E0351E30 (Ver. 3.0)

8

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