EBD10RD4ABFA Просмотр технического описания (PDF) - Elpida Memory, Inc
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EBD10RD4ABFA Datasheet PDF : 19 Pages
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EBD10RD4ABFA
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 1 1 07H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 1 0 0 0CH
Number of DIMM ranks
0 0 0 0 0 0 0 1 01H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
DDR SDRAM cycle time, CL = X
-6B
-7A, -7B
0 1 1 0 0 0 0 0 60H
0 1 1 1 0 1 0 1 75H
SDRAM access from clock (tAC)
-6B
-7A, -7B
0 1 1 1 0 0 0 0 70H
0 1 1 1 0 1 0 1 75H
DIMM configuration type
0 0 0 0 0 0 1 0 02H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 0 1 0 0 04H
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
SDRAM device attributes:
Minimum clock delay back-to-back
column access
0 0 0 0 0 0 0 1 01H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
0 0 0 0 1 1 0 0 0CH
0 0 0 0 0 0 0 1 01H
0 0 0 0 0 0 1 0 02H
SDRAM module attributes
0 0 1 0 0 1 1 0 26H
SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H
Minimum clock cycle time at CLX - 0.5
-6B, -7A
0
1
1
1
0
1
0
1
75H
-7B
1 0 1 0 0 0 0 0 A0H
Maximum data access time (tAC) from
clock at CLX - 0.5
0 1 1 1 0 0 0 0 70H
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
Minimum clock cycle time at CLX - 1 0 0 0 0 0 0 0 0 00H
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00H
Minimum row precharge time (tRP)
-6B
0
1
0
0
1
0
0
0
48H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Comments
128
256 byte
SDRAM DDR
13
12
1
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*3
0.70ns*3
0.75ns*3
ECC
7.8 µs
Self refresh
×4
×4
1 CLK
2, 4, 8
4
2/2.5
0
1
Registered
± 0.2V
CL = 2*3
0.70ns*3
0.75ns*3
18ns
20ns
Preliminary Data Sheet E0274E40 (Ver. 4.0)
5
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