DS28E10 Просмотр технического описания (PDF) - Maxim Integrated

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DS28E10

1-Wire SHA-1 Authenticator

Maxim Integrated 

ABRIDGED DATA SHEET

1-Wire SHA-1 Authenticator

1-Wire Signaling

The DS28E10 requires strict protocols to ensure data

integrity. The protocol consists of four types of signaling

on one line: reset sequence with reset pulse and pres-

ence pulse, write-zero, write-one, and read-data. Except

for the presence pulse, the bus master initiates all falling

edges. The DS28E10 can communicate at two different

speeds: standard speed and overdrive speed. If not

explicitly set into the overdrive mode, the DS28E10 com-

municates at standard speed. While in overdrive mode

the fast timing applies to all waveforms.

To get from idle to active, the voltage on the 1-Wire line

needs to fall from VPUP below the threshold VIL. To get

from active to idle, the voltage needs to rise from 0V

past the threshold VIH. The time it takes for the voltage

to make this rise is seen in Figure 9 as ε, and its dura-

tion depends on the pullup resistor (RPUP) used and the

capacitance of the 1-Wire network attached.

Figure 9 shows the initialization sequence required to

begin any communication with the DS28E10. A reset

pulse followed by a presence pulse indicates that the

DS28E10 is ready to receive data, given the correct

ROM and memory function command. If the bus master

uses slew-rate control on the falling edge, it must pull

down the line for tRSTL + tF to compensate for the edge.

A tRSTL duration of 480Fs or longer exits the overdrive

mode, returning the device to standard speed. If the

DS28E10 is in overdrive mode and tRSTL is no longer

than 80Fs, the device remains in overdrive mode. If the

device is in overdrive mode and tRSTL is between 80Fs

and 480Fs, the device resets, but the communication

speed is undetermined.

After the bus master has released the line it goes into

receive mode. Now the 1-Wire bus is pulled to VPUP

through the pullup resistor, or in case of a DS2482-x00

driver, by active circuitry. When the threshold VIH is

crossed, the DS28E10 waits for tPDH and then transmits

a presence pulse by pulling the line low for tPDL. To

detect a presence pulse, the master must test the logical

state of the 1-Wire line at tMSP.

The tRSTH window must be at least the sum of

tPDHMAX, tPDLMAX, and tRECMIN. Immediately after

tRSTH is expired, the DS28E10 is ready for data com-

munication. In a mixed population network, tRSTH should

be extended to minimum 480Fs at standard speed and

48Fs at overdrive speed to accommodate other 1-Wire

devices.

Read/Write Time Slots

Data communication with the DS28E10 takes place in

time slots, which carry a single bit each. Write time slots

transport data from bus master to slave. Read time slots

transfer data from slave to master. Figure 10 illustrates

the definitions of the write and read time slots.

All communication begins with the master pulling the

data line low. As the voltage on the 1-Wire line falls below

the threshold VIL, the DS28E10 starts its internal timing

generator that determines when the data line is sampled

VPUP

VIHMASTER

VIH

VIL

0V

MASTER Tx "RESET PULSE"

tRSTL

tF

RESISTOR

MASTER Rx "PRESENCE PULSE"

ε

tMSP

tPDH

MASTER

tPDL

tRSTH

tREC

DS28E10

Figure 9. Initialization Procedure: Reset and Presence Pulse

17

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