DS2149 Просмотр технического описания (PDF) - Maxim Integrated

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DS2149

5V T1/J1 Line Interface Unit

Maxim Integrated 

DS2149

3. INITIALIZATION AND RESET

During power-up, all control registers are cleared, disabling the transmitter outputs. The device requires a

master clock supplied to the MCLK input pin to operate the PLL. This master clock must be independent,

free-running, and jitter free.

A reset initializes the status and state machines for the RCL, AIS, NLOOP, and QRSS blocks. Under

software control, setting the RESET bit (CR2.7) clears all registers. Allow up to 100ms for the receiver to

recover from initialization.

4. REGISTER DEFINITIONS

The DS2149 contains eight registers for configuring the device and reading status. These are accessible

using the serial port. Table 4-A lists the register names and addresses.

Reading or writing to the internal registers requires writing one address/command byte prior to

transferring register data. The first bit written (LSb) of the address/command byte specifies whether the

access is a read (1) or a write (0). The next 6 bits identify the register address.

The last bit (MSb) of the address/command byte is the burst mode bit. When the burst bit is enabled (set

to 1) and a READ operation is performed, addresses 10h through 17h are read sequentially, starting at

address 10h. And when the burst bit is enabled and a WRITE operation is performed, addresses 10h

through 17h are written sequentially, starting at address 10h. Burst operation is stopped once address 17h

is read. All data transfers are initiated by driving the CS input low. All data transfers are terminated if the

CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.

Table 4-A. Register Map

REGISTER

Control Register 1

Control Register 2

Control Register 3

Interrupt Mask Register

Transition Status Register

Status Register

Information Register

Control Register 4

SYMBOL

CR1

CR2

CR3

IMR

TSR

SR

IR

CR4

ADDRESS

B010000

B010001

B010010

B010011

B010100

B010101

B010110

B010111

Table 4-B. Register Bit Positions

SYMBOL

CR1

CR2

CR3

IMR

TSR

SR

IR

CR4

7 (MSb)

JASEL1

RESET

JA6HZ

Z16D

Z16D

—

RL3

—

6

JASEL0

PAT1

TPD

JALT

JALT

—

RL2

—

5

ENCENB

PAT0

—

DFMO

DFMO

DFMO

RL1

—

4

3

UNIENB

L3

TAIS

ENLOOP

EQZMON20 EQZMON26

B8ZSD

QRSS

B8ZSD

QRSS

—

QRSS

RL0

LUP

—

—

2

L2

ALB

JA128

AIS

AIS

AIS

LDN

RCL2048

Note: Set unused bits to 0 for normal operation.

1

L1

LLB

LIRST

NLOOP

NLOOP

NLOOP

TSCD

XFMR2

0 (LSb)

L0

RLB

TAOZ

RCL

RCL

RCL

LOTC

XFMR1

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