DS1878 Просмотр технического описания (PDF) - Maxim Integrated
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DS1878 Datasheet PDF : 101 Pages
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SFP+ Controller with Digital LDD Interface
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (Figure 19)
PARAMETER
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and START
Condition
START Hold Time
START Setup Time
Data In Hold Time
Data In Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
STOP Setup Time
Capacitive Load for Each Bus Line
EEPROM Write Time
SYMBOL
CONDITIONS
fSCL
tLOW
tHIGH
(Note 12)
tBUF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
CB
tWR
(Note 13)
(Note 13)
(Note 14)
MIN TYP
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
20 + 0.1CB
0.6
MAX
400
0.9
300
300
400
20
UNITS
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
pF
ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +5.5V, unless otherwise noted.)
PARAMETER
EEPROM Write Cycles
SYMBOL
At +25°C
At +85°C
CONDITIONS
MIN TYP
200,000
50,000
MAX UNITS
Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: Eight ranges allow the full-scale range to change from 312mV to 1.25V.
Note 4: The output impedance of the device is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance is 1.5kΩ.
Note 5: This parameter is guaranteed by design.
Note 6: Full-scale is programmable.
Note 7: A temperature conversion is completed and the MODULATION register value is recalled from the LUT and VCC has been
measured to be above the VCC LO alarm.
Note 8: The timing is determined by the choice of the SAMPLE RATE setting (see Table 02h, Register 88h).
Note 9: This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
Note 10: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 11: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be within 3% within the time specified by the binary search time. See the BIAS and MODULA-
TION Control During Power-Up section.
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard-mode timing.
Note 13: CB—the total capacitance of one bus line in pF.
Note 14: EEPROM write begins after a STOP condition occurs.
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