1339RR-2 Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

Список матч

1339RR-2

I2C Serial Real-Time Clock

Maxim Integrated 

DS1339 I2C Serial Real-Time Clock

POWER-UP/DOWN CHARACTERISTICS

(TA = -40°C to +85°C) (Note 1, Figure 1)

PARAMETER

SYMBOL

CONDITIONS

Recovery at Power-Up

tREC

(Note 15)

VCC Fall Time; VPF(MAX) to VPF(MIN)

tVCCF

VCC Rise Time; VPF(MIN) to VPF(MAX)

tVCCR

MIN TYP MAX UNITS

2

ms

300

µs

0

µs

WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in

battery-backup mode.

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

Note 13:

Note 14:

Note 15:

Limits at -40°C are guaranteed by design and are not production tested.

SCL only.

SDA and SQW/INT.

ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled.

Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled.

VCC must be less than 3.63V if the 250Ω resistor is selected.

Using recommended crystal on X1 and X2.

After this period, the first clock pulse is generated.

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line

is released.

CB—total capacitance of one bus line in pF.

Guaranteed by design. Not production tested.

The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤

VCC ≤ VCCMAX and 1.3V ≤ VBACKUP ≤ 3.7V.

This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.

Figure 1. Power-Up/Down Timing

VPF(MVACXC)

VPF(MIN)

t VCCF

INPUTS

RECOGNIZED

DON'T CARE

t VCCR

tREC

RECOGNIZED

OUTPUTS

VALID

HIGH-Z

VALID

5 of 19

Share Link: