DM9010 Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

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DM9010

10/100 Mbps Single Chip Ethernet Controller with General Processor Interface

Davicom Semiconductor, Inc. 

DM9010

Single Chip Ethernet Controller with General Processor Interface

6.47 MEMORY DATA WRITE COMMAND WITH ADDRESS INCREMENT REGISTER (F8H)........................................................ 28

6.48 MEMORY DATA WRITE_ADDRESS REGISTER (FAH~FBH).......................................................................................... 28

6.49 TX PACKET LENGTH REGISTER (FCH~FDH)............................................................................................................. 28

6.50 INTERRUPT STATUS REGISTER (FEH) ......................................................................................................................... 28

6.51 INTERRUPT MASK REGISTER (FFH)............................................................................................................................ 29

7. EEPROM FORMAT........................................................................................................................................................ 30

8. MII REGISTER DESCRIPTION ................................................................................................................................... 31

8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00 .......................................................................................................... 32

8.2 BASIC MODE STATUS REGISTER (BMSR) - 01.............................................................................................................. 33

8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02 ........................................................................................................ 35

8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03 ........................................................................................................ 35

8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04 ................................................................................... 35

8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05................................................................... 36

8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER)- 06 ............................................................................................. 37

8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16 ................................................................................. 38

8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17.......................................................... 39

8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18.............................................................................................. 40

8.11 POWER DOWN CONTROL REGISTER (PWDOR) - 19 ................................................................................................... 41

8.12 (SPECIFIED CONFIG) REGISTER – 20 ............................................................................................................................ 42

9. FUNCTIONAL DESCRIPTION..................................................................................................................................... 43

9.1 HOST INTERFACE .......................................................................................................................................................... 43

9.2 DIRECT MEMORY ACCESS CONTROL............................................................................................................................ 43

9.3 PACKET TRANSMISSION................................................................................................................................................ 43

9.4 PACKET RECEPTION...................................................................................................................................................... 43

9.5 100BASE-TX OPERATION............................................................................................................................................. 44

9.5.1 4B5B Encoder ...................................................................................................................................................... 44

9.5.2 Scrambler ............................................................................................................................................................. 44

9.5.3 Parallel to Serial Converter................................................................................................................................. 44

9.5.4 NRZ to NRZI Encoder .......................................................................................................................................... 44

9.5.5 MLT-3 Converter ................................................................................................................................................. 44

9.5.6 MLT-3 Driver....................................................................................................................................................... 44

9.5.7 4B5B Code Group ................................................................................................................................................ 45

Preliminary

4

Version: DM9010-17--DS-P04

Jan. 18, 2006

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