CY7C961 Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
CY7C961 Datasheet PDF : 7 Pages
| |||
CY7C960
CY7C961
To assist in generating the configuration file, a Win-
dows™-based program is available which guides the user through
the process of selecting appropriate options. Contact your Sales
Office for further details.
The CY7C961 is a true superset of the CY7C960. Signal pins
have been added to control CY7C964 DMA functions. Existing
VMEbus input pins have been changed to bidirectional and
augmented to complete a master interface. A data port and
chip select signal (SELECTLM*) complete the pin additions.
As a VMEbus Slave, the CY7C961 behaves in every respect
like the CY7C960. It simply has more pins, a master block
transfer facility, and (because of the addition of the BBSY*
connection) full lock cycle support.
From a system perspective, the CY7C961 master block trans-
fer capability can be viewed as a DMA channel that resides on
the slave card, but is controlled over the VMEbus by one or
more VMEbus masters or programmed from the local bus.
System Diagram Using the CY7C960
The CY7C961 master block facility provides “block transfer on
demand” capability for slave cards built around the Cypress
CY7C961/CY7C964 chipset. This facility allows one or many
VMEbus masters to write short series of commands to the
slave card, telling it how much data to move, where to get it
from, where to put it, and what transfer protocol to use while
moving it. Blocks can be moved over the VMEbus as indivisi-
ble single cycles or BLTs. The protocol menu includes D8,
D16, D32, MD32, or D64. A16, A24, A32, A40, and A64 ad-
dress spaces can be specified. Burst lengths from 16 bytes to
8 megabytes can be requested. Eight registers accessible
from the VMEbus make the facility simple to configure and
simple to control. The facility has a busy semaphore, a VME-
bus Interrupt on completion feature with a programmable Sta-
tus/ID byte, and a built in requester and bus grant daisychain.
DRAMMEMORY
LA [31:0]
DBE[3:0], RW
LACK*
RAS*, CAS*, ROW,COL
SWDEN
RW
SWAP
BUFFER
VCOMP
LA [31:0]
I/O
LIRQ*
CS[2:0]
DECODER
REGION
LA [7:1, LWORD]
CY7C964
CY7C964
CY7C964
CY7C964
CY7C960
VMEDATABUS
D[31:0]
VME ADDRESS BUS
A [31:1], LWORD*
VME INTERRUPT BUS
4
c960–5
Share Link: 