CY7C4285-15ASC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C4285-15ASC

32K/64Kx18 Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))

tCLKH

tCLKL

WCLK

WEN

tENS tENH

PAE

RCLK

REN

tSKEW3 [22]

Note 21

tPAE synch

N + 1 WORDS

IN FIFO

tENS

tENS tENH

CY7C4275

CY7C4285

Note 23 tPAE synch

Programmable Almost Full Flag Timing

4275–14

WCLK

WEN

tCLKH

Note 24

tCLKL

tENS tENH

PAF [25]

RCLK

REN

tPAF

FULL– M WORDS

IN FIFO[26]

FULL– (M+1) WORDS

IN FIFO [27]

tPAF

tENS

4275–15

Notes:

21. PAE offset − n.

22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the

rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.

23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.

24. PAF offset = m. Number of data words written into FIFO already = 32768 − (m + 1) for the CY7C4285 and 65536 − (m + 1) for the CY7C4285.

25. PAF is offset = m.

26. 32768 − m words in CY7C4275 and 65536 – m words in CY7C4285.

27. 32768 − (m + 1) words in CY7C4275 and 65536 – (m + 1) CY7C4285.

Document #: 38-06008 Rev. *A

Page 11 of 21

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