IDT71F432L66 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71F432L66 Datasheet PDF : 5 Pages
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IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
256KB CACHE BLOCK DIAGRAM
COMMERCIAL TEMPERATURE RANGE
PROCESSOR BUS
TAG
SRAM
CHIPSET
CACHE
CONTROLLER
CLK
ADSC#
CE#
OE#
ADV#
GW#
BWE#
F0, F1
CS0
CS1#
IDT71F432
32Kx32
IDT71F432
32Kx32
PIN DESCRIPTION SUMMARY
SYMBOL
A14 – A0
DESCRIPTION
Address Inputs
CE#
CS0, CS1#
OE#
GW#
BWE#
BW1#, BW2#, BW3#, BW4#
CLK
ADV#
ADSC#
ADSP#
I/O31-I/O0
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Data Input/Output
NC
NC
RESET#
W/R#
F0
F1
VDD5
VDD
VSS
Reserved for LBO# (burst order)
Reserved for ZZ (sleep)
Host Bus Reset Signal
Host Bus W/R#
Function 0
Function 1
5V Power
3.3V Power
Ground
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
NC
NC
Input
Input
Special
Special
Pwr
Pwr
Gnd
PIN NUMBER
48, 47, 46, 45, 44, 81, 82, 99,
100, 32, 33, 34, 35, 36, 37
98
97, 92
86
88
87
93, 94, 95, 96
89
83
85
84
29, 28, 25, 24, 23, 22, 19, 18, 13, 12,
9, 8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72,
69, 68, 63, 62, 59, 58, 57, 56, 53, 52
31
64
38
39
43
42
16, 66
4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91
5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 77
3555 tbl 01
13.1
2
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