Timing Waveforms (continued)
Write Cycle 2 (CE controlled) [14, 16, 17]
Address
CE
tSA
WE
Data In/Out
High Z
CY7C199CN
tWC
tSCE
tHA
tAW
tSD
tHD
Data-In Valid
High Z
Notes
13. This cycle is WE controlled, OE is HIGH during write.
14. Data in and/or out is high impedance if OE = VIH.
15. During this period the IOs are in output state and input signals must not be applied.
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document #: 001-06435 Rev. *E
Page 11 of 18
[+] Feedback