CY7C1487V25 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1487V25 Datasheet PDF : 30 Pages
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CY7C1481V25
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CY7C1487V25
Pin Definitions (continued)
Pin Name
VDD
VDDQ
VSS
VSSQ[2]
MODE
TDO
TDI
TMS
TCK
NC
I/O
Power Supply
I/O Power
Supply
Ground
I/O Ground
Input-Static
JTAG Serial
Output
Synchronous
JTAG Serial
Input
Synchronous
JTAG Serial
Input
Synchronous
JTAG Clock
-
Description
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the core of the device.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not used, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not used, this pin can be left floating or connected to VDD through a pull up
resistor. This pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not used, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are
address expansion pins are not internally connected to the die.
Note
2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.
Document #: 38-05281 Rev. *H
Page 8 of 30
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