AD8108AST(1997) Просмотр технического описания (PDF) - Analog Devices
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AD8108AST Datasheet PDF : 28 Pages
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AD8108/AD8109
TIMING CHARACTERISTICS (Parallel)
Parameter
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
–
–
–
Limit
Min
Max
20
100
20
100
0
50
8
100
200
1
CLK
0
1
D0–D3
A0–A2
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t4
t1
t3
Figure 2. Timing Diagram, Parallel Mode
t5 t6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table II. Logic Levels
VIH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
2.0 V min
VIL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
VOH
DATA OUT
VOL
DATA OUT
0.8 V max
2.7 V min 0.5 V max
IIH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
20 µA max
IIL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
IOH
DATA OUT
–400 µA min
–400 µA max
IOL
DATA OUT
3.0 mA min
–4–
REV. 0
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