CY7C1352B-80AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1352B-80AC Datasheet PDF : 12 Pages
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PRELIMINARY
CY7C1352B
Switching Characteristics Over the Operating Range[11, 12, 13]
-166
-150
-143
-133
-100
-80
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
Clock Cycle Time
5.0
6.6
7.0
7.5
10
12.5
ns
tCH
Clock HIGH
1.4
2.5
2.8
3.0
4.0
4.0
ns
tCL
Clock LOW
1.4
2.5
2.8
3.0
4.0
4.0
ns
tAS
Address Set-Up Before CLK 1.5
1.5
2.0
2.0
2.2
2.5
ns
Rise
tAH
Address Hold After CLK Rise 0.5
0.5
0.5
0.5
0.5
1.0
ns
tCO
Data Output Valid After CLK
3.5
3.8
4.0
4.2
5.0
7.0 ns
Rise
tDOH
Data Output Hold After CLK 1.5
1.5
1.5
1.5
1.5
1.5
ns
Rise
tCENS
CEN Set-Up Before CLK Rise 1.5
1.5
2.0
2.0
2.2
2.5
ns
tCENH
CEN Hold After CLK Rise 0.5
0.5
0.5
0.5
0.5
1.0
ns
tWES
GW, BWS[1:0] Set-Up Before 1.5
1.5
2.0
2.0
2.2
2.5
ns
CLK Rise
tWEH
GW, BWS[1:0] Hold After CLK 0.5
0.5
0.5
0.5
0.5
1.0
ns
Rise
tALS
ADV/LD Set-Up Before CLK 1.5
1.5
2.0
2.0
2.2
2.5
ns
Rise
tALH
ADV/LD Hold after CLK Rise 0.5
0.5
0.5
0.5
0.5
1.0
ns
tDS
Data Input Set-Up Before
1.5
1.5
1.7
1.7
2.0
2.5
ns
CLK Rise
tDH
Data Input Hold After CLK 0.5
0.5
0.5
0.5
0.5
1.0
ns
Rise
tCES
Chip Enable Set-Up Before 1.5
1.5
2.0
2.0
2.2
2.5
ns
CLK Rise
tCEH
tCHZ
tCLZ
tEOHZ
Chip Enable Hold After CLK 0.5
0.5
0.5
0.5
0.5
1.0
ns
Rise
Clock to High-Z[10, 12, 13, 14] 1.5 3.2 1.5 3.2 1.5 3.5 1.5 3.5 1.5 3.5 1.5 5.0 ns
Clock to Low-Z[10, 12, 13, 14] 1.5
1.5
1.5
1.5
1.5
1.5
ns
OE HIGH to Output High-Z[10,
3.0
3.0
4.0
4.2
5.0
7.0 ns
12, 13, 14]
tEOLZ
OE LOW to Output Low-Z[10, 0
12, 13, 14]
0
0
0
0
0
ns
tEOV
OE LOW to Output Valid[12]
Shaded areas contain advance information.
3.2
3.5
4.0
4.2
5.0
7.0 ns
Notes:
12. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads and waveforms. Transition is measured ± 200 mV
from steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
8
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