CY7C1351 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1351

128Kx36 Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

Switching Waveforms

Read/Write/Deselect Sequence

CY7C1351

CLK

tCENS

CEN

tCENH

tCH tCL

tCYC

tCENS

tCENH

tAS

ADDRESS RA1

WA2

RA3

tAH

WE

tWS tWH

RA4

WA5

RA6

RA7

tCES

CE

tCEH

tCLZ

tDOH

tCHZ

Data-

In/Out

Q1

D2

Q3

Out

In

Out

Device

originally

deselected

tCDV

tDOH

Q4

D5

Q6

Out

In

Out

tCHZ

Q7

Out

WE is the combination of WE & BWSx to define a write cycle (see Write Cycle Description table).

CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select

the device. Any chip select can deselect the device. RAx stands for Read Address X, WAx stands for

Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.

= DON’T CARE

= UNDEFINED

10

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