CY7C1339G(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1339G Datasheet PDF : 17 Pages
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PRELIMINARY
CY7C1339G
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17]
250 MHz 200 MHz 166 MHz 133 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the first Access[12]
Min. Max Min. Max Min. Max Min. Max Unit
1
1
1
1
ms
tCYC
Clock Cycle Time
tCH
Clock HIGH
tCL
Clock LOW
Output Times
4.0
5.0
6.0
7.5
ns
1.7
2.0
2.5
3.0
ns
1.7
2.0
2.5
3.0
ns
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[13, 14, 15]
Clock to High-Z[13, 14, 15]
OE LOW to Output Valid
OE LOW to Output Low-Z[13, 14, 15]
OE HIGH to Output High-Z[13, 14, 15]
2.6
2.8
3.5
4.0 ns
1.0
1.0
1.5
1.5
ns
0
0
0
0
ns
2.6
2.8
3.5
4.0 ns
2.6
2.8
3.5
4.0 ns
0
0
0
0
ns
2.6
2.8
3.5
4.0 ns
tAS
Address Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise 1.2
1.2
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
tCES
Chip Enable Set-Up Before CLK Rise
1.2
1.2
1.5
1.5
ns
Hold Times
tAH
Address Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tADH
ADSP , ADSC Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tWEH
GW,BWE, BWX Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
Shaded areas contain advance information.
Notes:
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write
operation can be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the
same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is
designed to achieve High-Z prior to Low-Z under the same system conditions
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05520 Rev. *A
Page 10 of 17
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