datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

MB91121PFV Просмотр технического описания (PDF) - Fujitsu

Номер в каталоге
Компоненты Описание
Список матч
MB91121PFV
Fujitsu
Fujitsu Fujitsu
MB91121PFV Datasheet PDF : 97 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
MB91121
s BLOCK DIAGRAM
FR CPU
RAM (4 KB)
Bit Search Module
3
DREQ0 to DREQ2
DACK0 to DACK2
EOP0 to EOP2
3 DMAC (8 ch)
3
DSP macro
(Embedded RAM 4 )
Bus Converter (32 bit 16 bit)
X0
X1
RST
Clock Control Unit
(Watct Dog Timer)
INT0 to INT7
NMI
8 Interrupt Control
Unit
AN0 to AN7
AVCC
AVRH
AVSS /AVRL
8
10 bit A/D
Converter (8 ch)
Instruction Cache (1 KB)
Bus Converter
(HarvardPrinceton)
Bus Controller
16
25
D16 to D31
A00 to A24
RDY
2
WR0 to WR1
RDY
6
CLK
CS0 to CS5
BRQ
BGRNT
DRAM Controller
RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1
Port 0 to Port B
Reload Timer (3 ch)
Port
STRG
Soft DMA Start Circuit
UART (3 ch)
with
Baud Rate Timer
3
3
3
SI0 to SI2
SO0 to SO2
SC0 to SC2
PWM Timer (4 ch)
4 OCPA0 to OCPA3
4 TRG0 to TRG3
Note : Pins are display for functions (Actually some pins are multiplexer) .
When using REALOS, time control should be done by using external interrupt or inner timer.
16

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]