CY7C1313AV18-250BZC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1313AV18-250BZC Datasheet PDF : 22 Pages
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PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
Truth Table[ 2, 3, 4, 5, 6, 7]
Operation
K
Write Cycle:
L-H
Load address on the rising
edge of K; input write data on
two consecutive K and K
rising edges.
Read Cycle:
L-H
Load address on the rising
edge of K; wait one and a
half cycle; read data on two
consecutive C and C rising
edges.
NOP: No Operation
L-H
RPS
H[8]
WPS
L[9]
DQ
D(A) at
K(t+1) ↑
L[9]
X
Q(A) at
C(t +1)↑
H
H
D=X
Q=High-Z
DQ
D(A + 1) at
K(t+1) ↑
DQ
DQ
D(A + 2) at K(t D(A + 3) at
+ 2) ↑
K(t +2) ↑
Q(A + 1) at
C(t + 2) ↑
Q(A + 2) at C(t Q(A + 3) at C(t
+ 2)↑
+ 3) ↑
D=X
Q=High-Z
D=X
Q=High-Z
D=X
Q=High-Z
Standby: Clock Stopped Stopped X
X
Previous State Previous State Previous
Previous State
State
Write Cycle Descriptions CY7C1311AV18 and CY7C1313AV18) [2, 10]
BWS0 BWS1 K K
Comments
L
L L–H – During the Data portion of a Write sequence :
CY7C1311AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313AV18 − both bytes (D[17:0]) are written into the device.
L
L – L-H During the Data portion of a Write sequence :
CY7C1311AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313AV18 − both bytes (D[17:0]) are written into the device.
L
H L–H – During the Data portion of a Write sequence :
CY7C1311AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1313AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
L
H – L–H During the Data portion of a Write sequence :
CY7C1311AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1313AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
H
L L–H – During the Data portion of a Write sequence :
CY7C1311AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1313AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
H
L – L–H During the Data portion of a Write sequence :
CY7C1311AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1313AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
H
H L–H – No data is written into the devices during this portion of a write operation.
H
H – L–H No data is written into the devices during this portion of a write operation.
Notes:
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t”
clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1311AV18 and CY7C1313AV18 and also
BWS2, BWS3 in the case of CY7C1315AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05498 Rev. *A
Page 8 of 22
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