CY7C1313AV18-200BZC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1313AV18-200BZC Datasheet PDF : 22 Pages
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PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
Single Clock Mode
The CY7C1313AV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1313AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. If the ports access the same location
when a read follows a write in successive clock cycles, the
SRAM will deliver the most recent information associated with
the specified address location. This includes forwarding data
from a Write cycle that was initiated on the previous K clock
rise.
Read accesses and Write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
Application Example[1]
Depth Expansion
The CY7C1313AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon powerup to account for drifts in supply voltage and
temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the QDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
SRAM #1
R = 250ohms
ZQ
Vt
RW B
CQ/CQ#
D
PPW
SS S
Q
R
A
# # # C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC) Source K#
Delayed K
Delayed K#
R R = 50ohms Vt = Vddq/2
Note:
1. The above application shows four QDRII being used.
SRAM #4
ZQ R = 250ohms
RW B
CQ/CQ#
D
PPW
SS S
Q
A
## #
C C# K K#
Vt
Vt
R
Document #: 38-05498 Rev. *A
Page 7 of 22
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