CY7C1313AV18 Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C1313AV18 Datasheet PDF : 22 Pages
| |||
PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
AC Electrical Characteristics Over the Operating Range
Parameter
Description
VIH
Input High (Logic 1) Voltage
VIL
Input Low (Logic 0) Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
–
–
Max. Unit
–
V
VREF – 0.2 V
Switching Characteristics Over the Operating Range[18,19]
Cypress Consortium
Parameter Parameter
Description
250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Unit
tCYC
tKH
tKL
tKHKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
4.0 5.25 5.0 6.3 6.0 8.4 ns
1.6 – 2.0
2.4 – ns
1.6 – 2.0 – 2.4 – ns
1.8 – 2.2 – 2.7 – ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0 1.8 0.0 2.3 0.0 2.8 ns
rising edge)
Set-up Times
tSA
tSA
tSC
tSC
Address Set-up to K Clock Rise
0.5 – 0.6 – 0.7 – ns
Control Set-up to Clock (K, K, C, C) Rise (RPS, 0.5 – 0.6 – 0.7 – ns
WPS)
tSCDDR
tSC
tSD
tSD
Hold Times
Double Data Rate Control Set-up to Clock (K, K) 0.35 – 0.4 – 0.5 – ns
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Set-up to Clock (K/K) Rise
0.35 – 0.4 – 0.5 – ns
tHA
tHA
tHC
tHC
tHCDDR
tHC
tHD
tHD
Output Times
Address Hold after Clock (K/K) Rise
0.5 – 0.6 – 0.7 – ns
Control Hold after Clock (K /K) Rise (RPS, WPS) 0.5 – 0.6 – 0.7 – ns
Double Data Rate Control Hold after Clock (K/K) 0.35 – 0.4 – 0.5 – ns
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Hold after Clock (K/K) Rise
0.35 – 0.4 – 0.5 – ns
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to – 0.45 – 0.45 – 0.50 ns
Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise –0.45 – -0.45 – -0.50 – ns
(Active to Active)
tCCQO
tCQOH
tCQD
tCQDOH
tCHZ
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHZ
tCLZ
tCLZ
DLL Timing
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C and C) Rise to High-Z (Active to
High-Z)[20, 21]
Clock (C and C) Rise to Low-Z[20, 21]
– 0.45 – 0.45 – 0.50 ns
–0.45 – –0.45 – –0.50 – ns
– 0.30 – 0.35 – 0.40 ns
–0.30 – –0.35 – –0.40 – ns
– 0.45 – 0.45 – 0.50 ns
–0.45 – –0.45 – –0.50 – ns
tKC Var
tKC Var
Clock Phase Jitter
– 0.20 – 0.20 – 0.20 ns
tKC lock
tKC lock
DLL Lock Time (K, C)
1024 – 1024 – 1024 – cycles
tKC Reset tKC Reset
K Static to DLL Reset
30
30
30
ns
Notes:
18. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequncy,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
20. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
21. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document #: 38-05498 Rev. *A
Page 11 of 22
Share Link: 