CY7C1313AV18-200BZC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1313AV18-200BZC Datasheet PDF : 22 Pages
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PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
Maximum Ratings (Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied .. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.5V
DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch-up Current..................................................... >200 mA
Operating Range
Range
Com’l
Ambient
Temperature(TA)
0°C to +70°C
VDD[16]
1.8 ± 0.1V
VDDQ[16]
1.4V to VDD
DC Electrical Characteristics Over the Operating Range[11]
Parameter
Description
VDD
VDDQ
VOH
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
[12]
Min.
1.7
1.4
VDDQ/2
-0.12
Typ.
1.8
1.5
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
Output LOW Voltage
[13]
VDDQ/2
-0.12
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[14]
Input LOW Voltage[14,15]
IOH = −0.1 mA, Nominal Impedance
IOL = 0.1mA, Nominal Impedance
VDDQ – 0.2
VSS
VREF + 0.1
–0.3
Clock Input Voltage
–0.3
Input Load Current
Output Leakage Current
Input Reference Voltage[17]
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
−5
−5
0.68
VDD Operating Supply
VDD = Max., IOUT = 0
mA,
f = fMAX = 1/tCYC
167 MHz
200 MHz
250 MHz
-
0.75
ISB1
Automatic
Power-down
Curren
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX =
1/tCYC,
Inputs Static
167 MHz
200 MHz
250 MHz
Notes:
11. All Voltage referenced to Ground.
12. Output are impedance controlled. Ioh=−(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms.
13. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms.
14. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
15. This spec is for all inputs except C and C clocks. For C and C clocks, VIL(Max.) = VREF − 0.2V.
16. Power-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
17. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
Max. Unit
1.9
V
VDD
V
VDDQ/2 + V
0.12
VDDQ/2 + V
0.12
VDDQ
V
0.2
V
VDDQ+0.3 V
VREF–0.1 V
VDDQ + 0.3 V
5
µA
5
µA
0.95
V
640
mA
700
mA
800
mA
420
mA
450
mA
490
mA
Document #: 38-05498 Rev. *A
Page 10 of 22
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