CY7C1215H Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1215H Datasheet PDF : 15 Pages
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CY7C1215H
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage on VDD Relative to GND....... –0.5V to + 4.6V
Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V
–5%/+10%
VDDQ
2.5V –5%
to VDD
Electrical Characteristics Over the Operating Range[7, 8]
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
for 3.3V I/O
for 2.5V I/O
VOH
Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
VOL
Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
VIH
Input HIGH Voltage[7] for 3.3V I/O
for 2.5V I/O
VIL
Input LOW Voltage[7] for 3.3V I/O
for 2.5V I/O
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
Current
f = fMAX = 1/tCYC
6-ns cycle,166 MHz
7.5-ns cycle, 133 MHz
ISB1
Automatic CS
VDD = Max, Device Deselected, 6-ns cycle,166 MHz
Power-down
VIN ≥ VIH or VIN ≤ VIL
7.5-ns cycle, 133 MHz
Current—TTL Inputs f = fMAX = 1/tCYC
ISB2
Automatic CS
VDD = Max, Device Deselected, All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CS
VDD = Max, Device Deselected, or 6-ns cycle,166 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 7.5-ns cycle, 133 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CS
VDD = Max, Device Deselected, All speeds
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Min.
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
–30
–5
–5
Max. Unit
3.6
V
VDD
V
2.625 V
V
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
µA
µA
5
µA
µA
30
µA
5
µA
240 mA
225 mA
100 mA
90
mA
40
mA
85
mA
75
mA
45
mA
Notes:
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05666 Rev. *B
Page 7 of 15
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