CY7C1009BN Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1009BN Datasheet PDF : 9 Pages
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AC Test Loads and Waveforms
R1 480Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 480Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
3.0V
GND
≤ 3 ns
CY7C109BN
CY7C1009BN
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics[5] Over the Operating Range
7C109BN-12 7C109BN-15 7C109BN-20
7C1009BN-12 7C1009BN-15 7C1009BN-20
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
12
15
20
ns
tAA
Address to Data Valid
12
15
20
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
6
7
8
ns
tLZOE
OE LOW to Low Z
0
0
0
ns
tHZOE
OE HIGH to High Z[6, 7]
6
7
8
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
3
3
3
ns
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7]
6
7
8
ns
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up 0
0
0
ns
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
12
15
20
ns
Write Cycle[8]
tWC
Write Cycle Time[9]
12
15
20
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End 10
12
15
ns
tAW
Address Set-Up to Write End
10
12
15
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
12
ns
tSD
Data Set-Up to Write End
7
8
10
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
0
0
0
ns
3
3
3
ns
6
7
8
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06430 Rev. **
Page 3 of 9
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