CY7C1032(1995) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1032
(Rev.:1995)

64K x 18 Synchronous Cache RAM

Cypress Semiconductor 

Switching Waveforms

Single Read[12]

tCH

CLK

CS

ADDRESS

ADSP [13]or

ADSC

[14]

WH, WL

DATA OUT

PRELIMINARY

tCL

tCSS

tCSH

tAS

tAH

tADS

tADSH

tWES

tWEH

tCYC

tCDV

Single Write Timing: Write Initiated by ADSP

tCH

CLK

tCSS

tCSH

CS

tAS

tAH

ADDRESS

ADSP

tADS

tADSH

[14]

WH, WL

DATA IN

DATA OUT

OE

tEOZ

Notes:

12. OE is LOW throughout this operation.

13. If ADSP is asserted while CS is HIGH, ADSP will be ignored.

14. ADSP has no effect on ADV, WL, and WH if CS is HIGH.

tCL

tWES

tWEH

tDS

tDH

8

CY7C1031

CY7C1032

tDOH

1031–6

1031–5

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