CY7C1049B(2006) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1049B Datasheet PDF : 9 Pages
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Switching Characteristics Over the Operating Range[4]
Parameter
Description
Read Cycle
tpower
VCC(typical) to the First Access[5]
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
-12
Min. Max.
1
12
12
3
12
6
0
6
3
6
0
12
12
10
10
0
0
10
7
0
3
6
-15
Min. Max.
1
15
15
3
15
7
0
7
3
7
0
15
15
12
12
0
0
12
8
0
3
7
CY7C1049B
-17
Min. Max. Unit
1
ms
17
ns
17
ns
3
ns
17
ns
8
ns
0
ns
7
ns
3
ns
7
ns
0
ns
17
ns
17
ns
12
ns
12
ns
0
ns
0
ns
12
ns
8
ns
0
ns
3
ns
8
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[11]
Min. Max. Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
tCDR[3]
tR[10]
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Com’l
L VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200 µA
0
ns
tRC
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation
is started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. tr < 3 ns for all the speeds
11. No input may exceed VCC + 0.5V.
Document #: 38-05169 Rev. *B
Page 4 of 9
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