CY7C1041B Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1041B

256K x 16 Static RAM

Cypress Semiconductor 

Data Retention Waveform

VCC

3.0V

tCDR

CE

DATA RETENTION MODE

VDR > 2V

CY7C1041B

3.0V

tR

Switching Waveforms

Read Cycle No. 1[12, 13]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[13, 14]

DATA VALID

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes:

12. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL.

13. WE is HIGH for read cycle.

14. Address valid prior to or coincident with CE transition LOW.

Document #: 38-05142 Rev. *A

Page 6 of 11

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