CY7C1021CV33-10 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1021CV33-10 Datasheet PDF : 12 Pages
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CY7C1021CV33
Switching Characteristics Over the Operating Range[5]
1021CV33-8 1021CV33-10 1021CV33-12 1021CV33-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
8
tAA
Address to Data Valid
tOHA
Data Hold from Address Change 3
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z[6]
0
tHZOE
OE HIGH to High-Z[6, 7]
tLZCE
CE LOW to Low-Z[6]
3
tHZCE
CE HIGH to High-Z[6, 7]
tPU[8]
CE LOW to Power-Up
0
tPD[8]
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
0
tHZBE
Byte Disable to High-Z
Write Cycle[9]
10
12
15
ns
8
10
12
15 ns
3
3
3
ns
8
10
12
15 ns
5
5
6
7
ns
0
0
0
ns
4
5
6
7
ns
3
3
3
ns
4
5
6
7
ns
0
0
0
ns
8
10
12
15 ns
5
5
6
7
ns
0
0
0
ns
4
5
6
7
ns
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
ns
tSD
Data Set-Up to Write End
5
5
6
8
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[6]
WE LOW to High-Z[6, 7]
0
0
0
0
ns
3
3
3
3
ns
4
5
6
7
ns
tBW
Byte Enable to End of Write
6
7
8
9
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05132 Rev. *C
Page 5 of 12
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