7C1002 Просмотр технического описания (PDF) - Cypress Semiconductor

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7C1002

256K x 4 Static RAM with Separate I/O

Cypress Semiconductor 

CY7C1001

PRELIMINARY CY7C1002

Switching Waveforms (continued)

Write Cycle No. 1 (CE Controlled)[9, 14]

ADDRESS

CE

tSA

WE

DATA IN

DATA OUT

(7C1002)

HIGH IMPEDANCE

DATA OUT

(7C1001)

Write Cycle No. 2 (WE Controlled)[9]

ADDRESS

CE

WE

DATA IN

DATA OUT

(7C1002)

DATA OUT

(7C1001)

tSA

tWC

tSCE

tAW

tPWE

tSD

DATA VALID

tADV

tLZCE

tDCE

tHA

tHD

tHZCE

DATA VALID

tWC

tSCE

tAW

tPWE

tHA

tSD

DATA VALID

tHD

tHZWE

tLZWE

HIGH IMPEDANCE

tDWE

tADV

tHZCE

DATA VALID

Note:

14. If CE goes HIGH simultaneously with WE going HIGH, the output

remains in a highĆimpedance state (7C1002 only).

C1001-8

C1001-9

5

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