CY7C109B-20 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C109B-20 Datasheet PDF : 10 Pages
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CY7C109B
CY7C1009B
AC Test Loads and Waveforms
R1 480Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 480Ω
ALL INPUT PULSES
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
3.0V
R2
255Ω
GND
≤ 3 ns
90%
10%
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
90%
10%
≤ 3 ns
Switching Characteristics[5]
Parameter
Description
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7]
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
Write Cycle[8]
tWC
Write Cycle Time[9]
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
7C109B-12
7C1009B-12
Min. Max.
12
12
3
12
6
0
6
3
6
0
12
12
10
10
0
0
10
7
0
3
6
7C109B-15
7C1009B-15
Min. Max.
15
15
3
15
7
0
7
3
7
0
15
15
12
12
0
0
12
8
0
3
7
7C109B-20
7C1009B-20
Min. Max. Unit
20
ns
20 ns
3
ns
20 ns
8
ns
0
ns
8
ns
3
ns
8
ns
0
ns
20 ns
20
ns
15
ns
15
ns
0
ns
0
ns
12
ns
10
ns
0
ns
3
ns
8
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05038 Rev. *C
Page 3 of 10
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