CY7C038V-20AXI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C038V-20AXI Datasheet PDF : 18 Pages
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
ADDRESS
Figure 7. Write Cycle No. 1: R/W Controlled Timing[20, 21, 22, 23]
tWC
OE
[24,25]
CE
R/W
DATA OUT
DATA IN
tAW
tSA
tPWE[23]
NOTE 27
tHZWE[26]
tSD
tHA
tLZWE
tHD
tHZOE[26]
NOTE 27
ADDRESS
[24,25]
CE
R/W
DATA IN
Figure 8. Write Cycle No. 2: CE Controlled Timing[20, 21, 22, 28]
tWC
tAW
tSA
tSCE
tHA
tSD
tHD
Notes
20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
22. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
24. To access RAM, CE = VIL, SEM = VIH.
25. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
26. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06078 Rev. *B
Page 10 of 18
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