CY7C026A-12AC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C026A-12AC

16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle No. 1: R/W Controlled Timing[25, 26, 27, 28]

tWC

ADDRESS

OE

[29,30]

CE

R/W

DATA OUT

DATA IN

tAW

tSA

tPWE[28]

NOTE 32

tHZWE[31]

tSD

Write Cycle No. 2: CE Controlled Timing[25, 26, 27, 33]

tWC

ADDRESS

[29,30]

CE

tSA

R/W

tAW

tSCE

tSD

DATA IN

CY7C026A

CY7C036A

tHZOE[31]

tHA

tLZWE

tHD

NOTE 32

tHA

tHD

Notes:

25. R/W must be HIGH during all address transitions.

26. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

27. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

28. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified tPWE.

29. To access RAM, CE = VIL, SEM = VIH.

30. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.

To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

31. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

32. During this period, the I/O pins are in the output state, and input signals must not be applied.

33. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

Document #: 38-06046 Rev. *C

Page 11 of 18

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