CY7C026A(2000) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C026A Datasheet PDF : 17 Pages
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CY7C026A
CY7C036A
Switching Characteristics Over the Operating Range[9] (continued)
Parameter
BUSY TIMING[16]
Description
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[17]
BUSY HIGH to Data Valid
INTERRUPT TIMING[16]
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CY7C026A
CY7C036A
-12[1]
-15
-20
Min. Max. Min. Max. Min. Max. Unit
12
15
20
ns
12
15
20
ns
12
15
20
ns
12
15
17
ns
5
5
5
ns
0
0
0
ns
11
13
15
ns
12
15
20
ns
12
15
20
ns
12
15
20
ns
10
10
10
ns
5
5
5
ns
5
5
5
ns
12
15
20
ns
Data Retention Mode
The CY7C026A and CY7C036A are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
Timing
VCC
CE
Data Retention Mode
4.5V
VCC > 2.0V
4.5V
VCC to VCC – 0.2V
tRC
VIH
Parameter
ICCDR1
Test Conditions[18]
@ VCCDR = 2V
Max.
1.5
Unit
mA
Notes:
16. Test conditions used are Load 2.
17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
18. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
8
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