CY7C008V(2010) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C008V
(Rev.:2010)

3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM

Cypress Semiconductor 

CY7C008V/009V

CY7C018V/019V

Data Retention Mode

The CY7C008V/009V and CY7C018V/019V are designed with

battery backup in mind. Data retention voltage and supply

current are guaranteed over temperature. The following rules

ensure data retention:

1. Chip enable (CE) must be held HIGH during data retention,

within VCC to VCC – 0.2 V.

2. CE must be kept between VCC – 0.2 V and 70% of VCC during

the power-up and power-down transitions.

3. The RAM can begin operation > tRC after VCC reaches the

minimum operating voltage (3.0 V).

Timing

VCC

CE

Data Retention Mode

3.0 V VCC 2.0 V 3.0 V

tRC

VCC to VCC – 0.2 V

VIH

Parameter

ICCDR1

Test Conditions[22]

@ VCCDR = 2 V

Max

50

Unit

A

Note

22. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.

Document Number: 38-06044 Rev. *E

Page 10 of 23

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