CY7C006A-20(2010) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

Список матч

CY7C006A-20
(Rev.:2010)

32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM

Cypress Semiconductor 

CY7C006A/CY7C007A

CY7C016A/CY7C017A

Contents

Pin Configurations ........................................................... 3

Selection Guide ................................................................ 4

Pin Definitions .................................................................. 5

Architecture ...................................................................... 5

Functional Description ..................................................... 5

Write Operation ........................................................... 5

Read Operation ........................................................... 5

Interrupts ..................................................................... 5

Busy ............................................................................ 6

Master/Slave ............................................................... 6

Semaphore Operation ................................................. 6

Maximum Ratings ............................................................. 7

Operating Range ............................................................... 7

Electrical Characteristics ................................................. 7

Capacitance Table ............................................................ 8

AC Test Loads and Waveforms ....................................... 8

AC Test Loads (Applicable to –12 only) ......................... 8

Switching Characteristics ................................................ 9

Data Retention Mode ...................................................... 10

Timing .............................................................................. 10

Switching Waveforms .................................................... 11

Read Cycle No. 1 (Either Port Address Access) ....... 11

Read Cycle No. 2 (Either Port CE/OE Access) ......... 11

Read Cycle No. 3 (Either Port) .................................. 11

Write Cycle No. 1: R/W Controlled Timing ................ 12

Write Cycle No. 2: CE Controlled Timing .................. 12

Semaphore Read After Write Timing, Either Side ..... 13

Timing Diagram of Semaphore Contention ............... 13

Timing Diagram of Read with BUSY (M/S=HIGH) .... 14

Write Timing with Busy Input (M/S=LOW) ................. 14

CELValid First: ........................................................... 15

Left Address Valid First: ............................................ 15

Busy Timing Diagram No. 1 (CE Arbitration) ............. 15

Busy Timing Diagram No. 2 (Address Arbitration) .... 15

Interrupt Timing Diagrams ......................................... 16

Ordering Information ...................................................... 18

16K x 8 Asynchronous Dual-Port SRAM ................... 18

Ordering Code Definitions ......................................... 18

Package Diagrams .......................................................... 19

Document History Page ................................................. 21

Sales, Solutions, and Legal Information ...................... 22

Worldwide Sales and Design Support ....................... 22

Products .................................................................... 22

PSoC Solutions ......................................................... 22

Document Number: 38-06045 Rev. *F

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