CY7C006A-20JXC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C006A-20JXC Datasheet PDF : 22 Pages
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics
Over the Operating Range[14]
Parameter
Description
–12[15]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–15
Unit
–20
Min Max Min Max Min Max
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
tACE[16]
Output Hold From Address Change
CE LOW to Data Valid
tDOE
tLZOE[17, 18, 19]
tHZOE[17, 18, 19]
tLZCE[17, 18, 19]
tHZCE[17, 18, 19]
tPU[19]
tPD[19]
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
WRITE CYCLE
12
–
15
–
20
–
ns
–
12
–
15
–
20
ns
3
–
3
–
3
–
ns
–
12
–
15
–
20
ns
–
8
–
10
–
12
ns
3
–
3
–
3
–
ns
–
10
–
10
–
12
ns
3
–
3
–
3
–
ns
–
10
–
10
–
12
ns
0
–
0
–
0
–
ns
–
12
–
15
–
20
ns
tWC
tSCE[16]
Write Cycle Time
CE LOW to Write End
tAW
Address Valid to Write End
tHA
tSA[16]
Address Hold From Write End
Address Set-Up to Write Start
tPWE
Write Pulse Width
tSD
Data Set-Up to Write End
tHD[22]
Data Hold From Write End
tHZWE[18, 19]
R/W LOW to High Z
tLZWE[18, 19]
R/W HIGH to Low Z
tWDD[20]
Write Pulse to Data Delay
tDDD[20]
Write Data Valid to Read Data Valid
BUSY TIMING[21]
12
–
15
–
20
–
ns
10
–
12
–
15
–
ns
10
–
12
–
15
–
ns
0
–
0
–
0
–
ns
0
–
0
–
0
–
ns
10
–
12
–
15
–
ns
10
–
10
–
15
–
ns
0
–
0
–
0
–
ns
–
10
–
10
–
12
ns
3
–
3
–
3
–
ns
–
25
–
30
–
45
ns
–
20
–
25
–
30
ns
tBLA
BUSY LOW from Address Match
–
12
–
15
–
20
ns
tBHA
BUSY HIGH from Address Mismatch
–
12
–
15
–
20
ns
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
15. See page 7 for Load Conditions.
16. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
18. Test conditions used are Load 3.
19. This parameter is guaranteed but not tested.
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
22. For 15 ns industrial parts tHD Min. is 0.5 ns.
Document Number: 38-06045 Rev. *F
Page 9 of 22
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