CY62128V25 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62128V25

128K x 8 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]

ADDRESS

CE1

tWC

tSCE

CE2

WE

tSCE

tAW

tSA

tPWE

OE

DATA I/O

NOTE 15

tHZOE

tSD

DATAIN VALID

Truth Table

CE1 CE2 OE WE

I/O0–I/O7

H

X

X

X High Z

Power-Down

Mode

X

L

X

X High Z

Power-Down

L

H

L

H Data Out

Read

L

H

X

L Data In

Write

L

H

H

H High Z

Selected, Outputs Disabled

Note:

15. During this period, the I/Os are in output state and input signals should not be applied.

CY62128V Family

tHA

tHD

62128V-11

Power

Standby (ISB)

Standby (ISB)

Active (ICC)

Active (ICC)

Active (ICC)

7

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