CY62128VLL-70ZAC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62128VLL-70ZAC

128K x 8 Static RAM

Cypress Semiconductor 

CY62128V Family

Switching Waveforms

Read Cycle No. 1[10, 11]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[11, 12]

ADDRESS

tRC

CE1

CE2

OE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]

DATA VALID

62128V–8

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

50%

ICC

ISB

62128V-9

ADDRESS

CE1

CE2

WE

DATA I/O

tWC

tSCE

tSA

tSCE

tAW

tHA

tPWE

tSD

tHD

DATA VALID

Notes:

10. Device is continuously selected. OE, CE = VIL, CE2=VIH.

11. WE is HIGH for read cycle.

12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

13. Data I/O is high impedance if OE = VIH.

14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.

62128V-10

6

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