CY22801KSXC-XXX(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY22801KSXC-XXX
(Rev.:2011)

Universal Programmable Clock Generator (UPCG)

Cypress Semiconductor 

CY22801

2-wire Serial (I2C) Interface Timing

When using I2C interface, the CY22801 should be programmed

as I2C-capable prior to using this interface.

The CY22801 uses a 2-wire serial-interface SDAT and SCLK

that operates up to 400 kbits/second in read or write mode. The

basic write serial format is as follows.

Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); eight-bit Memory Address (MA); ACK;

eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK;

eight-bit data in MA+2; ACK; and so on, until STOP bit. The basic

serial format is illustrated in Figure 14.

Data Valid

Data is valid when the Clock is HIGH, and may only be

transitional when the clock is LOW, as illustrated in Figure 13.

Data Frame

Start Sequence – Start frame is indicated by SDAT going LOW

when SCLK is HIGH. Every time a Start signal is given, the next

eight-bit data must be the device address (seven bits) and a R/W

bit, followed by the register address (eight bits) and register data

(eight bits).

Stop Sequence – Stop frame is indicated by SDAT going HIGH

when SCLK is HIGH. A Stop frame frees the bus for writing to

another part on the same bus or writing to another random

register address.

Acknowledge Pulse

During Write mode, the CY22801 responds with an ACK pulse

after every eight bits. This is accomplished by pulling the SDAT

line LOW during the N*9th clock cycle, as illustrated in Figure 16.

(N = the number of eight-bit segments transmitted.) During Read

mode, the ACK pulse, after the data packet is sent, is generated

by the master.

Every new data frame is indicated by a start and stop sequence,

as illustrated in Figure 15.

Figure 13. Data Valid and Data Transition Periods

Data valid Transition to next bit

SDAT

CLKHIGH

VIH

SCLK

VIL

tDH tSU

CLKLOW

Figure 14. Data Frame Architecture

SDAT Write

Multiple

Contiguous

Registers

1-bit 1-bit

1-bit Slave Slave

R/W = 0 ACK ACK

1-bit

Slave

ACK

1-bit

Slave

ACK

7-bit

8-bit 8-bit 8-bit 8-bit

Device Register Register Register Register

Address Address Data Data Data

(XXH) (XXH) (XXH+1) (XXH+2)

Start Signal

1-bit 1-bit 1-bit

Slave Slave Slave

ACK ACK ACK

8-bit 8-bit

Register Register

Data Data

(FFH) (00H)

1-bit

Slave

ACK

Stop Signal

SDAT Read

Multiple

Contiguous

Registers

1-bit 1-bit

1-bit

1-bit Slave Slave 1-bit Master

R/W = 0 ACK ACK R/W = 1 ACK

7-bit

8-bit

8-bit 8-bit

Device Register 7-Bit Register Register

Address Address Device Data Data

(XXH) Address (XXH) (XXH+1)

Start Signal

1-bit 1-bit 1-bit

Master Master Master

ACK ACK ACK

8-bit 8-bit

Register Register

Data Data

(FFH) (00H)

1-bit

Master

ACK

Stop Signal

Document #: 001-15571 Rev. *E

Page 17 of 23

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