CXK5V8257BTM/BYM/BM
• Write cycle (2): CE control
Address
OE
CE
WE
Data in
tWC
tAW
tAS
tCW
tWR1(∗3)
tWP
tDW
tDH
Data valid
Data out
High impedance
∗1 Write is executed when both CE and WE are at low simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.
∗3 tWR1 is measured at the period from the rising edge of CE to the end of write cycle.
–6–