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CXA2027

Analog signal processor IC

Sony Semiconductor 

CXA2027Q

Pulse Timing

[Pulse Timing 1 (pixel units)]

CLP pulse and SH pulse

Input the SH pulse at the end of the effective signal so as not to be affected by signal fluctuation caused by

the clamp.

SH pulse and MPX pulse (MPX1, MPX2)

Input the SH pulse in sync with the reference channel.

MPX1 pulse and MPX2 pulse

Delay the timing of MPX2 when G changes to B. (Table 1, t3)

CCD signal

(R-IN/

G-IN/

B-IN)

Reset level

Precharge level

CLP

t2

SH

50%

t4

t1

50%

Effective signal level

MPX1

MPX2

50%

t3

50%

tr = tf = 5ns

SIGOUT

t5

Data taken in at

AD converter

Output channel B

R

G

B

R

Min.

Typ.

Max.

t1

100ns

t2

40ns

50ns

t3

5ns

20ns

t4

5ns

t5

60ns

Table 1

– 11 –

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