CS8416-DZZR Просмотр технического описания (PDF) - Cirrus Logic

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CS8416-DZZR

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

2.2 QFN Pin Description

CS8416

RXP0 1

RXN 2

VA 3

AGND 4

FILT 5

RST 6

RXP4 7

28 27 26 25 24 23 22

Thermal Pad

Top-Down View

28-pin QFN Package

21 RMCK

20 VD

19 DGND

18 VL

17 GPO0

16 GPO1

15 AD2 / GPO2

8 9 10 11 12 13 14

Pin

Name

VA

VD

VL

AGND

DGND

RST

FILT

Pin #

Pin Description

3

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise

as possible since noise on this pin will directly affect the jitter performance of the recovered clock

20 Digital Power (Input) – Digital core power supply. Nominally +3.3 V

18 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

4

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-

nected to a common ground area under the chip.

19

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected

to a common ground area under the chip.

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.

6 On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable

in frequency and phase.

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

5 For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on

page 53 for more information on the PLL and the external components.

14

DS578F3

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