CS8416-CNZ Просмотр технического описания (PDF) - Cirrus Logic
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CS8416-CNZ Datasheet PDF : 60 Pages
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2. PIN DESCRIPTION - SOFTWARE MODE
2.1 TSSOP Pin Description
RXP3
RXP2
RXP1
RXP0
RXN
VA
AGND
FILT
RST
RXP4
RXP5
RXP6
RXP7
AD0 / CS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
Top-Down View
17
28-pin SOIC/TSSOP
13
Package
16
14
15
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
GPO0
GPO1
AD2 / GPO2
SDA / CDOUT
SCL / CCLK
AD1 / CDIN
CS8416
Pin
Name
VA
VD
VL
AGND
DGND
RST
FILT
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
Pin #
Pin Description
6
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise
as possible since noise on this pin will directly affect the jitter performance of the recovered clock
23 Digital Power (Input) – Digital core power supply. Nominally +3.3 V
21 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
7
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
22
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected
to a common ground area under the chip.
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.
9 On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.
8 For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on
page 53 for more information on the PLL and the external components.
4
3
2
1
10
11
12
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select
line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-
ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-
ommended input circuits.
13
12
DS578F3
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